Design Verification Engineer

Key responsibilities

• Develop and execute verification strategies for ASIC/SoC designs.
• Build and enhance SystemVerilog/UVM testbenches, test cases and verification environments.
• Define or update block-level and full-chip verification plans.
• Run simulations and regressions, investigate failures and coordinate defect resolution.
• Analyze functional and code coverage and drive verification closure.
• Perform gate-level simulation and support projects through tape-out.
• Participate in design reviews and ensure verification work follows established quality processes.

• Support and mentor other engineers where appropriate.

Requirements

• Develop and execute verification strategies for ASIC/SoC designs.
• Build and enhance SystemVerilog/UVM testbenches, test cases and verification environments.
• Define or update block-level and full-chip verification plans.
• Run simulations and regressions, investigate failures and coordinate defect resolution.
• Analyze functional and code coverage and drive verification closure.
• Perform gate-level simulation and support projects through tape-out.
• Participate in design reviews and ensure verification work follows established quality processes.
• Support and mentor other engineers where appropriate.

HOW TO APPLY: Please send your CV to the consultant in charge:

Ms. Thao Tran

E-mail: thao.tran@ev-search.com

All applications will be considered without regard to race, color, religion, sex (including pregnancy and gender identity), national origin, political affiliation, sexual orientation, marital status, disability, genetic information, age, membership in an employee organization, parental status, military service, or any other non-merit factor.