Key responsibilities
- Design, implement and validate dft solutions, including mbist, scan chains, boundary scan and atpg.
- Build, optimize and maintain dft flows using siemens/mentor tessent.
- Monitor test coverage, identify and resolve dft-related issues, and support design closure.
- Review technical deliverables to ensure quality and alignment with project requirements.
- Collaborate with cross-functional engineering teams to identify technical risks and achieve project milestones.
- Provide technical guidance and support to junior engineers when required.
Requirements
- Bachelor’s degree in electronics, electrical engineering, computer engineering or a related field.
- Minimum 2 years of experience in dft or a relevant ic design role.
- Hands-on experience with mbist, scan insertion, boundary scan and atpg verification.
- Practical experience with the tessent dft toolchain.
- Understanding of asic/soc development and tape-out processes.
- Strong analytical, troubleshooting and problem-solving skills.
- Good working proficiency in english.
- Willingness to undertake overseas assignments, including potential opportunities in Japan.
HOW TO APPLY: Please send your CV to the consultant in charge:
E-mail: thao.tran@ev-search.com
All applications will be considered without regard to race, color, religion, sex (including pregnancy and gender identity), national origin, political affiliation, sexual orientation, marital status, disability, genetic information, age, membership in an employee organization, parental status, military service, or any other non-merit factor.
