Key responsibilities
- Perform physical implementation from RTL or gate-level netlist through GDSII.
- Take ownership of assigned blocks or design partitions throughout the back-end flow.
- Handle floorplanning, power planning, placement, clock-tree synthesis and routing.
- Drive timing, signal-integrity and power closure to meet sign-off requirements.
- Resolve DRC, LVS and IR-drop issues and prepare designs for tape-out.
- Collaborate with front-end, DFT and verification teams during design integration and closure.
- Develop scripts to automate and improve physical design workflows
Requirements
- Bachelor’s degree or above in Electronics, Electrical Engineering, Computer Engineering or an equivalent field.
- At least 2 years of experience in ASIC physical design or back-end implementation.
- Experience with Cadence Innovus, Synopsys IC Compiler II or Fusion Compiler.
- Familiarity with timing and power tools such as PrimeTime, Tempus, Voltus or PowerReplay.
- Exposure to physical verification platforms such as Calibre, Pegasus or IC Validator.
- Understanding of netlist-to-GDSII flow, STA, CTS and physical sign-off.
- Knowledge of multi-Vt, multi-voltage, low-power and DFT-aware implementation is preferred.
- Experience with advanced process nodes is an advantage.
- Ability to automate engineering tasks using Python, Perl or Shell.
- Good command of English.
HOW TO APPLY: Please send your CV to the consultant in charge:
E-mail: thao.tran@ev-search.com
All applications will be considered without regard to race, color, religion, sex (including pregnancy and gender identity), national origin, political affiliation, sexual orientation, marital status, disability, genetic information, age, membership in an employee organization, parental status, military service, or any other non-merit factor.
